1. Field of the Invention
The present invention relates to a serial communication device, and more particularly to a serial communication device which can handle the errors of communication speeds and prevent the receive data detection errors due to noise.
2. Description of the Related Art
As a means of communication between a host computer and an external processor, UART (Universal Asynchronous Receiver Transmitter) serial communication is widely used. In the case of UART serial communication, the transmission side and the reception side do not perform data communication according to a common synchronous clock, but the data communication speed is set in advance, and the reception side judges the receive data by the sampling clock matching with the communication speed. Therefore a mismatch of the data communication speed (cycle) and the cycle of the sampling clock becomes a problem in judging the receive data.
FIG. 1 is a diagram depicting the principle of UART serial communication. The serial communication device in an external processor connected with a host computer via a serial communication cable starts sampling detection of receive data RDX when receiving the start bit STAB which is a 1-bit L level signal inserted at the beginning of 8-bit serial data DATA, for example, and detects the H level or L level of receive data RDX with synchronizing with the H level of the sampling clock SMP-CLK. When parity bit PAB and H level stop bit STOB, which are inserted after the 8-bit serial data DATA, are detected, one frame of serial communication is completed. In non-communicating status, the data signal is maintained to H level.
In this way, the cycle of the sampling clock SMP-CLK must be matched with the serial communication speed (cycle) of the receive data, and normally the cycle of the sampling clock is set according to a predetermined specification of the communication speed at the design stage.
FIG. 2 is a block diagram depicting a conventional serial communication device. This serial communication device is comprised of the receiver unit 10, transmitter unit 20 and communication clock generation unit 30 for supplying the clock for communication to these units. The receive data RDX received from the serial communication path, which is not illustrated, is received by the data receive circuit 12, then the receive data is detected synchronizing with the communication clock C-CLK or sampling clock SMP-CLK supplied from the communication clock generation unit 30, and is converted into the parallel data 14S by the serial-parallel conversion circuit 14. The transmission target parallel data 24S is converted into serial data by the parallel-serial conversion circuit 24, and the communication drive circuit 22 drives the transmission data signal TDX with synchronizing with the communication clock C-CLK.
Such a UART serial communication device is disclosed in Japanese Patent Application Laid-Open No. 11-275175, and Japanese Patent Application Laid-Open No. 2002-51034, for example.
FIG. 3 is a diagram depicting the problems of a conventional serial communication device. In the case of UART serial communication, transmission and reception do not share synchronous clocks, but serial data is transmitted/received asynchronously. Therefore the reception side must detect data at the sampling clock with the cycle matching with the communication speed (cycle of serial data). However, the sampling clock is generated by dividing the reference clock at the reception side, and the cycle does not always perfectly match with the communication speed (cycle). Therefore, as FIG. 3 shows, even if the sampling clock SMP-CLK is generated responding to the detection of the start bit STAB, the timing of the sampling clock and the timing of each bit of serial data may be shifted within one frame if an error exists between the cycle of serial data and the cycle of sampling clock, and in this case a reception error occurs.
To solve this problem, Japanese Patent Application Laid-Open No. 2002-51034 proposes to make the generation timing of the sampling clock to be changeable to any timing. However such a change of timing is implemented by software processing, and this processing becomes a burden, and a circuit for changing timing is also required.